The demand for online systems and services has driven an unprecedented growth in the network infrastructure to support such demand. To satisfy such growth, manufacturers of server equipment have developed increasingly complex server configurations. As the server systems have become more complex, manufacturers of such systems have received increasing pressure to improve the manageability of such systems.
In an effort to address this pressure, server management systems were developed. A server management system is typically composed of hardware, firmware and software embedded within a server system for the purpose of autonomous monitoring, recovery and control of a server's operation. Preferably, this server manageability is performed independently of the main processor(s), BIOS, and operating system of the server. The ultimate goal of server management is to lower the end-user's total cost of ownership (TCO).
An example of just such a server management architecture is detailed in the Intelligent Platform Management Interface (IPMI) specification or, more formally the IPMI—Intelligent Platform Management Interface Specification v1.5, Document Revision 1.0 Feb. 21, 2001, by Intel et al. The IPMI specification, which is incorporated herein by reference for all purposes, describes an architecture of hardware and firmware that monitors and controls a server platform independently of, but responsive to, the main processors and System Management Software (SMS). The IPMI is based on an addressable serial bus communication architecture. An example of a conventional IPMI architecture implementation is presented with reference to FIG. 1.
Turning briefly to FIG. 1, an example of a conventional IPMI architecture 100 is presented. As shown, the conventional IPMI architecture 100 is presented comprising a baseboard control element 102 coupled to a number of satellite control elements 104–110 through a single Intelligent Platform Management Bus (IPMB) 112. As indicated above, the IPMB 112 is typically implemented as an addressable serial bus such as, for example, the Inter-Integrated Circuit (I2C) serial bus and associated communication protocol developed by the semiconductor element of the Royal Philips Electronics N.V. based in the Netherlands, with a regional headquarters in New York, N.Y.
In the IPMI architecture 100 depicted in FIG. 1, the baseboard control element 102 can monitor a myriad of operational aspects affecting/detailing the health of the server system through any one or more of the satellite controller(s) 104–110. In certain implementations, the satellite control elements 104–110 may represent a combination of sensors, control logic, and the like used to monitor and control certain aspects of the server system.
Those skilled in the art will recognize, however, that one of the strengths of platform management architectures such as, e.g., the IPMI architecture, is the relative simplicity of the conventional interconnection structure. This simplicity brings with it a number of limitations, however. First, as a single-bus architecture, a failure of one of the control elements may well bring down (or, “hang”) the entire bus. In our IPMI example, above, the conventional IPMB architecture fails to provide adequate fault isolation for the IPMI system.
Second, the IPMB protocol employs a simple seven-bit address scheme to uniquely identify each of the elements on the IPMB. In a conventional IPMI architecture, a single baseboard control element, i.e., the master controller for the entire chassis is given the address of 20 Hex. Insofar as each element within the conventional IPMI system must be uniquely identifiable, and the baseboard control element must have the address of 20 H, such a limitation stipulates that a conventional IPMI system is limited to but a single baseboard control element. As mentioned above, however, complex server systems may well house servers for a number of different clients/purposes within a single chassis. The limitation of a single baseboard control element, described above, would prohibit implementation of a baseboard control element for each of the disparate servers within a chassis. Third, extending the limitations of the seven-bit address scheme, conventional IPMB implementations fail to provide for multiple address domains to, for example, provide secure manageability within each of a plurality of disparate servers populating a server chassis.
Finally, the conventional platform management architectures fail to offer virtual addressing, thereby permitting multiple elements coupled with the conventional interconnect to share a common physical address. Accordingly, an enhanced platform management architecture and associated methods is required, unencumbered by the inherent limitations commonly associated with the prior art. Just such a solution is provided in the discussion to follow.